1. Field of Invention
The present invention relates generally to technology for operating an operational amplifier using a switched capacitor circuit, and relates more particularly to technology for a clock signal generating device, generating method, and signal processing device for supplying clock signals to a switched capacitor circuit.
2. Description of Related Art
Switched capacitor circuits that provide high speed operation and occupy little space are needed for such applications as use in the amplifier stage of a pipeline A/D converter. As operating speed increases and device size decreases, the timing requirements of the clock signal used to operate the switched capacitor circuit become increasingly critical.
FIG. 8 is a circuit diagram of a common clock signal generating circuit for generating the clock signals φ1p, φ1Pp, φ2p, φ2Pp for operating an operational amplifier using a switched capacitor circuit. This clock signal generating circuit includes NAND circuits 1ap, 1bp, 1cp, 1dp, and a plurality of logic devices rendered by inverters 2ap, 2bp, 2cp, 2dp, 2ep, 2fp, 2gp, 2hp, 2ip, 2jp, 2kp, 2lp, 2mp, 2np.
FIG. 9 is a timing chart of clock signals φ1p, φ1Pp, φ2p, φ2Pp.
A bottom plate sampling period and a non-overlapping period are provided in a switched capacitor circuit to prevent the adverse effects of charge accumulation in the parasitic capacitance when the switch switches. An arrangement according to the related art for generating these periods is described next.
The timing of the bottom plate sampling period T1Lp required at the falling edge of clock signal φ1Pp and the falling edge of clock signal φ1p is determined by the total delay of logic devices 2bp, 2cp, 2dp.
The timing of the non-overlapping period T2Np required at the falling edge of clock signal φ1p and the rising edge of clock signal φ2p is determined by the total delay of logic devices 2ep, 2fp, 2gp.
Likewise, the timing of the bottom plate sampling period T2Lp required at the falling edge of clock signal φ2Pp and the falling edge of clock signal φ2p is determined by the total delay of logic devices 2ip, 2jp, 2kp.
The timing of the non-overlapping period T1Np required at the failing edge of clock signal φ2p and the rising edge of clock signal φ1p is determined by the total delay of logic devices 2lp, 2mp, 2np.
The clock signals CLKp and ICLKp input from input pins 3ap, 3bp are thus processed and output from output pins 4ap, 4bp, 4cp, 4dp at the timing of clock signals φ1Pp, φ1p, φ2Pp, φ2p, respectively.
The arrangement of the logic devices 2bp, 2cp, 2dp, 2ep, 2fp, 2gp, 2ip, 2jp, 2kp, 2lp, 2mp, 2np for setting the bottom plate sampling periods T1Lp and T2Lp and non-overlapping periods T1Np and T2Np is shown in FIG. 10. This is a common inverter circuit, and the transistors 7dp, 8bp rendering the inverter pass operating current between power supply node 3cp and ground node 3dp, take a clock signal input to node 3ep and output a clock signal from node 4ep. If the transistors are large, more operating current passes through the circuit, the response rate is faster, and the delay per logic device is shorter. Conversely, if the transistors are small, less operating current passes the circuit, the response rate is slower, and the delay per logic device is longer. The required bottom plate sampling periods T1LP and T2Lp and non-overlapping periods T1Np and T2Np can therefore be set by adjusting the size of the transistors.
The circuit shown in FIG. 8 uses three logic devices each to set the timing between clock signal φ1Pp and clock signal φ1p, the timing between clock signal φ1p and φ2p, the timing between clock signal φ2Pp and clock signal φ2p, and the timing between clock signal φ2p and clock signal φ1p. The required bottom plate sampling periods T1Lp and T2Lp and non-overlapping periods T1Np and T2Np can also be set by increasing the number of stages of these three element logic devices.
See, for example, U.S. Patent Application Publication No. 2005/0018061 (corresponding to Japanese Unexamined Patent Application Publication No. 2005-45786).
When the switched capacitor circuit and the clock signal generating circuit such as shown in FIG. 8 are provided on the same circuit board, variation in the logic devices and the parasitic resistance and parasitic capacitance components on the clock traces result in variation in the bottom plate sampling period and non-overlapping period. When a switched capacitor circuit is accelerated, the clock period is shorter and the effect of such variations is extremely great. This disrupts the timing of the bottom plate sampling period and non-overlapping period, and causes a signal offset in the operation of the switched capacitor circuit.
Furthermore, when the required bottom plate sampling period and non-overlapping period are set by adjusting the transistor size or increasing the number of logic device stages, depending upon the length of the required bottom plate sampling period and non-overlapping period, the area occupied by the logic devices for setting the bottom plate sampling period and non-overlapping period on the circuit board increases and could require using a larger circuit board.